The present invention relates to the field of semiconductor devices and circuits, and more specifically an improved system and method for selectively producing a clock or inverted clock signal.
Clock circuits and their use are well known in a wide variety of integrated circuit devices. It is often desirable in such devices to provide the ability to select between a clock signal and its inverse for use in a particular portion of an integrated circuit. Logic devices are exemplary of integrated circuits that use a clock signal and in which it is desirable to provide the ability to use the inverted version of the clock signal under selected circumstances. Programmable logic devices (sometimes referred to as PLDs, PALs, PLAs, FPLAs, PLDs, EPLDs EEPLDs, LCAs, or FPGAs) are a particular type of logic device that often provide for selection of a clock or an inverted clock in particular portions of a circuit therein. Such clock signals are used, for example, in flip-flops that provide registered output from such logic devices.
In one common embodiment, a clock signal is selectively inverted under the control of a memory bit. For example, a DRAM, EPROM, EEPROM, SRAM, or other stored data bit is used to control whether a circuit utilizes the clock or inverted clock signal. For example, in one type of programmable logic device, a clock is used in the operation of a flip-flop associated with a logic macrocell or logic array block (LAB). Based on the value stored in an SRAM bit, the device is able to selectively use either a global clock signal or its inverse in the flip-flop.
FIGS. 1A and 1B illustrate one prior circuit for selectively generating either a clock signal or its inverted value, and a specific use thereof. As shown in FIG. 1A, the output of a clock invert selection circuit 101 is used in a flip-flop 103. Flip-flop 103 may, for example, register output from programmable logic 105. A multiplexer 107 is used to select between registered and non-registered output from the flip-flop or the logic, respectively.
According to the clock invert selection circuit shown in more detail in FIG. 1B, the clock signal CLK is input to the circuit and its inverse is produced by an inverter I1. A RAM control bit 2 generates a RAM control signal RC and its inverse NRC. RC is provided at the gate of an NMOS transistor 3 while NRC (the inverted value of RC) is provided at the gate of an NMOS transistor 4. If RC is high, transistor 3 passes the value of CLK to a node 5. If RC is low, transistor 4 passes the inverted value of the clock signal to node 5.
The selected clock signal is usually buffered from external circuits by, for example, placing an inverter I2 at the output of the selection circuit. In most cases it is then desirable to regenerate both the selected clock signal and its inverse for usage in such external circuits. Accordingly, a node 6 provides the output signal C1, and provides input to an inverter I3, which provides the complementary output signal C2.
While meeting with substantial success, prior clock invert selection circuits have also met with certain limitations. For example, the gate delays of prior circuits have imposed speed limitations on such circuits. In particular, the circuit illustrated above generates a single output signal at node 6, from which the positive and negative values of the clock must be regenerated, which introduces extra gate delays. If such clock invert circuits operated more quickly, the operation of logic devices and other integrated circuits could be enhanced.
Accordingly, it is seen that an improved clock invert selection circuit is desired.